Traditionally, hardware accelerators are designed using Register Transfer Level (RTL) description languages such as Verilog. This can be both time-consuming and error-prone. Thus, using High-Level Synthesis for hardware design has attracted a lot of attention as an alternative. HLS enables designers to specify the hardware using behavioral-level languages like C/C++.

It is essential to produce different circuit designs to vary optimization parameters, like latency or design size, to meet variable resource constraints. In the context of HLS, this can be done through program transformation. There has already been work on source code transformation to optimize the latency of circuits synthesized by HLS. However, there is limited work on scaling the output circuit based on circuit size constraints. We aim to bridge this gap by discovering opportunities for resource reuse at the source code level.

Our approach is centered around the concept of loop saturation. Loop saturation uses e-graphs to synthesize loops from straight-line code, and optimize their structure using HLS feedback for the best latency-resource tradeoff.

The goal of our source code transformations is to improve design space exploration by automatically analyzing and rewriting code targeted by HLS. That way, developers can automatically produce more designs that fulfill varied hardware constraints.