Software-defined hardware design, also known as high-level synthesis (HLS), automatically translates a software program in a high-level language into a low-level hardware description. The software representation of a hardware design allows existing software optimization techniques to be applied at the algorithm level for efficient hardware synthesis. However, the hardware designs produced by these tools still suffer from a significant performance gap compared to manual implementations. This is because the input programs must still be written using hardware design principles.

Existing techniques either leave the program source unchanged or perform a fixed sequence of source transformation passes, potentially missing opportunities to find the optimal design. Our prior work proposes an efficient approach named SEER (Super-optimization Exploration using E-graph Rewriting) for software-defined hardware design that automatically rewrites a software algorithm into a representation that can be used to generate an efficient hardware design. SEER provides an extensible framework, orchestrating existing software compiler passes and hardware optimizers. In this paper, we would like to share the learned lessons and future challenges about algorithm-aware hardware optimizations using e-graph rewriting.